CPU 速通系列 4-1：MEM 模块

 1`include "defines.svh"
 2
 3module mem (
 4
 5    input logic rst,
 6
 7    //来自执行阶段的信息
 8    input logic [`RegAddrBus] wd_i,
 9    input logic               wreg_i,
10    input logic [    `RegBus] wdata_i,
11    input logic [    `RegBus] hi_i,
12    input logic [    `RegBus] lo_i,
13    input logic               whilo_i,
14
15    //送到回写阶段的信息
16    output logic [`RegAddrBus] wd_o,
17    output logic               wreg_o,
18    output logic [    `RegBus] wdata_o,
19    output logic [    `RegBus] hi_o,
20    output logic [    `RegBus] lo_o,
21    output logic               whilo_o
22
23);
24
25
26    always_comb begin
27        if (rst == `RstEnable) begin
28            wd_o    = `NOPRegAddr;
29            wreg_o  = `WriteDisable;
30            wdata_o = `ZeroWord;
31            hi_o    = `ZeroWord;
32            lo_o    = `ZeroWord;
33            whilo_o = `WriteDisable;
34        end else begin
35            wd_o    = wd_i;
36            wreg_o  = wreg_i;
37            wdata_o = wdata_i;
38            hi_o    = hi_i;
39            lo_o    = lo_i;
40            whilo_o = whilo_i;
41        end  //if
42    end  //always
43
44
45endmodule