CPU 速通系列 3-3：EX-MEM 模块

 1`include "defines.svh"
 2
 3module ex_mem (
 4
 5    input logic clk,
 6    input logic rst,
 7
 8    //来自控制模块的信息
 9    input logic [5:0] stall,
10
11    //来自执行阶段的信息
12    input logic [`RegAddrBus] ex_wd,
13    input logic               ex_wreg,
14    input logic [    `RegBus] ex_wdata,
15    input logic [    `RegBus] ex_hi,
16    input logic [    `RegBus] ex_lo,
17    input logic               ex_whilo,
18
19    input logic [`DoubleRegBus] hilo_i,
20    input logic [          1:0] cnt_i,
21
22    //送到访存阶段的信息
23    output logic [`RegAddrBus] mem_wd,
24    output logic               mem_wreg,
25    output logic [    `RegBus] mem_wdata,
26    output logic [    `RegBus] mem_hi,
27    output logic [    `RegBus] mem_lo,
28    output logic               mem_whilo,
29
30    output logic [`DoubleRegBus] hilo_o,
31    output logic [          1:0] cnt_o
32
33);
34
35    always_ff @(posedge clk) begin
36        if (rst == `RstEnable) begin
37            mem_wd    <= `NOPRegAddr;
38            mem_wreg  <= `WriteDisable;
39            mem_wdata <= `ZeroWord;
40            mem_hi    <= `ZeroWord;
41            mem_lo    <= `ZeroWord;
42            mem_whilo <= `WriteDisable;
43            hilo_o    <= {`ZeroWord, `ZeroWord};
44            cnt_o     <= 2'b00;
45        end else if (stall[3] == `Stop && stall[4] == `NoStop) begin
46            mem_wd    <= `NOPRegAddr;
47            mem_wreg  <= `WriteDisable;
48            mem_wdata <= `ZeroWord;
49            mem_hi    <= `ZeroWord;
50            mem_lo    <= `ZeroWord;
51            mem_whilo <= `WriteDisable;
52            hilo_o    <= hilo_i;
53            cnt_o     <= cnt_i;
54        end else if (stall[3] == `NoStop) begin
55            mem_wd    <= ex_wd;
56            mem_wreg  <= ex_wreg;
57            mem_wdata <= ex_wdata;
58            mem_hi    <= ex_hi;
59            mem_lo    <= ex_lo;
60            mem_whilo <= ex_whilo;
61            hilo_o    <= {`ZeroWord, `ZeroWord};
62            cnt_o     <= 2'b00;
63        end else begin
64            hilo_o <= hilo_i;
65            cnt_o  <= cnt_i;
66        end  //if
67    end  //always
68
69
70endmodule